The present disclosure of invention relates generally to monolithic integrated circuits, and more specifically to a repeated macrocell module design for use within Programmable Logic Devices (PLD""s).
The disclosure relates even more specifically to a macrocell module design as applied to a subclass of PLD""s known as Complex Programmable Logic Devices (CPLD""s) and High-Density Complex Programmable Logic Devices (HCPLD""s).
After this disclosure is lawfully published, the owner of the present patent application has no objection to the reproduction by others of textual and graphic materials contained herein provided such reproduction is for the limited purpose of understanding the present disclosure of invention and of thereby promoting the useful arts and sciences. The owner does not however disclaim any other rights that may be lawfully associated with the disclosed materials, including but not limited to, copyrights in any computer program listings or art works or other works provided herein, and to trademark or trade dress rights that may be associated with coined terms or art works provided herein and to other otherwise-protectable subject matter included herein or otherwise derivable herefrom.
If any disclosures are incorporated herein by reference and such incorporated disclosures conflict in part or whole with the present disclosure, then to the extent of conflict, and/or broader disclosure, and/or broader definition of terms, the present disclosure controls. If such incorporated disclosures conflict in part or whole with one another, then to the extent of conflict, the later-dated disclosure controls.
Field-Programmable Logic Devices (FPLD""s) have continuously evolved to better serve the unique needs of different end-users. From the time of introduction of simple PLD""s such as the Advanced Micro Devices 22V10(trademark) Programmable Array Logic device (PAL), the art has branched out in several different directions.
One evolutionary branch of FPLD""s has branched out along a paradigm known as Complex PLD""s or CPLD""s. This paradigm is characterized by devices such as the ispMACH(trademark) family (available from Lattice Semiconductor Corp. of Oregon). Examples of CPLD circuitry are seen in U.S. Pat. No. 5,015,884 (issued May 14, 1991 to Om P. Agrawal et al.) and U.S. Pat. No. 5,151,623 (issued Sep. 29, 1992 to Om P. Agrawal et al.) as well as in other CPLD patents cited above, including U.S. Pat. No. 6,150,841 which will be specifically addressed herein.
A CPLD device may be characterized as being constituted by a monolithic, integrated circuit (IC) that typically has four major features as follows.
(1) A user-accessible, configuration-defining memory means, such as EPROM, EEPROM, anti-fused, fused, SRAM, or other, is provided in the CPLD device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory or SRAM is of course, a form of reprogrammable memory that can be differently programmed many times. Electrically Erasable and reProgrammable ROM or EEPROM is an example of nonvolatile reprogrammable memory. The configuration-defining memory of a CPLD device can be formed of a mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM). Typically it is of the nonvolatile, In-System reProgrammable (ISP) kind such as EEPROM.
(2) Input/Output means (IO""s) are provided for interconnecting internal circuit components of the CPLD device with external circuitry. The IO""s may have fixed configurations or they may include configurable features such as variable slew-output drivers whose characteristics may be fine tuned in accordance with user-provided configuration instructions stored in the configuration-defining memory means.
(3) Programmable Logic Blocks (PLB""s) are provided for carrying out user-programmed logic functions as defined by user-provided configuration instructions stored in the configuration-defining memory means. Typically, each of the many PLB""s of a CPLD has at least a Boolean sum-of-products generating circuit (e.g., an AND/OR array or an equivalent such as a NAND/NAND array) or a Boolean product-of-sums generating circuit (e.g., an OR/AND array or an equivalent such as a NOR/NOR array) that is user-configurable to define a desired Boolean function, xe2x80x94to the extent allowed by the number of product terms (PT""s) or sum terms (ST""s) that are combinable by that circuit.
Each PLB may have other resources such as input signal pre-processing resources and output signal post-processing resources. The output signal post-processing resources may include result storing and/or timing adjustment resources such as clock-synchronized registers. Although the term xe2x80x98PLBxe2x80x99 was adopted by early pioneers of CPLD technology, it is not uncommon to see other names being given to the repeated portion of the CPLD that carries out user-programmed logic functions and timing adjustments to the resultant function
(4) An interconnect network is generally provided for carrying signal traffic within the CPLD between various PLB""s and/or between various IO""s and/or between various IO""s and PLB""s. At least part of the interconnect network is typically user-configurable so as to allow for programmably-defined routing of signals between various PLB""s and/or IO""s in accordance with user-defined routing instructions stored in the configuration-defining memory means.
In contrast to FPGA""s, which are LUT-based PLD""s (where a LUT in this context is a user-programmable Look-Up Table), gate-based CPLD""s are generally recognized in the art as having a comparatively less-expansive capability of implementing a wide variety of functions, in other words, not being able to implement all Boolean functions for a given input space as can a LUT. CPLD""s however, are expected to provide their lesser variety of logic functions with comparatively higher throughput speeds (smaller signal-propagation delays). In other words, wide functionality is sacrificed to obtain shorter, pin-to-pin signal delays. Thus pin-to-pin delay is an important measure of CPLD performance. Also, because length of signal routings through the programmable interconnect of a CPLD is often arranged so it will not vary significantly despite different signal routings, CPLD""s are generally recognized as being able to provide relatively consistent signal delays whose values often do not vary substantially in spite of how the corresponding CPLD configuring software (the partitioning, placement and routing software which configures the CPLD) behaves. Many devices in the Lattice/Vantis ispMACH(trademark) family provide such a consistent signal delay characteristic under the trade name of SpeedLocking(trademark). The more generic term, Speed-Consistency will be used interchangeably herein with the term, SpeedLocking(trademark).
A newly evolving sub-branch of the growing families of CPLD devices is known as High-Density Complex Programmable Logic Devices (HCPLD""s). This sub-branch may be generally characterized as being constituted by monolithic IC""s that each have large numbers of I/O terminals (e.g., Input/Output pins) in the range of about 32 or more (e.g., 64, 96, 128, 192, 256, 320, etc.) and/or have large numbers of result-storing macrocell units in the range of about 32 or more (e.g., 64, 128, 256, 320, 512, 1024, etc.). The process of concentrating large numbers of I/O pins and/or large numbers of macrocells into a single CPLD device raises new challenges for achieving relatively broad functionality, high speed, and Speed-Consistency (SpeedLocking(trademark)) in the face of wide varieties of configuration software.
More detailed discussion regarding different HCPLD architectures (1, 2, or 3 level hierarchical interconnects) and interrelated topics (e.g., adaptability to configuration software) are provided in the above-cited U.S. Pat. No. 6,184,713. As such they will not be repeated here except to briefly note the following. Configuration software can produce different results, good or bad, depending in part on what broadness of functionalities, what routing flexibilities and what timing flexibilities are provided by the architecture of a target CPLD. The present disclosure focuses on how some minor sacrifices in broadness of functionalities can provide more timing flexibilities, where such improvements are made in repeated structures referred to herein as macrocell modules.
The macrocell modules of a CPLD are typically configured at the same time that other programmable resources of the CPLD are configured. When the CPLD-configuring software is confronted with a given design problem (a supplied design specification that is to be realized by one or more CPLD""s), the CPLD-configuring software typically cycles through a series of phases, that are referred to commonly as xe2x80x98synthesisxe2x80x99, xe2x80x98mappingxe2x80x99, xe2x80x98partitioningxe2x80x99, xe2x80x98placementxe2x80x99, and xe2x80x98routingxe2x80x99. Results can vary because differently designed CPLD""s can have differently designed PLB""s (and differently designed macrocell modules therein) with respectively different, logic-implementing capabilities, resource-utilization efficiencies, and/or signal-propagation timing control capabilities.
Partitioning and routing software operations typically have to account for the maximum size and speed of circuitry that each PLB is able to implement within the specific CPLD device and to further account for pin-to-pin delay in over-all implementation of the circuit design. If all goes well in the partitioning, placement, and routing phases, the CPLD configuring software may determine that it has found a workable xe2x80x98solutionxe2x80x99 comprised of a specific partitioning of the original circuit into placeable chunks, a specific set of primitive placements of the chunks into specific PLB""s, and a specific set of interconnect usage decisions (routings). The software can then deem its mission to be complete and it can use the placement and routing results to generate the configuring code (e.g., the configuration bit stream) that will be used to correspondingly configure the designated CPLD.
In various instances, the CPLD configuring software may find that it cannot complete its mission successfully on a first try. It may find, for example that the initially-chosen placement and routing strategies prevent time-critical signals from reaching their desired destinations quickly enough to satisfy timing requirements of the input logic specification. Moreover, if the CPLD does not have enough resources, the CPLD configuring software may find that it has exhausted CPLD resources (e.g., inter-block interconnect) without completing the to-be-implemented design. It is desirable, in view of this, to have a CPLD structure which features small signal propagation times for implementing speed-critical parts of the to-be-implemented circuit, and in contradiction to this first desire, to have a CPLD structure which has the ability to densely implement various logic functions such that CPLD resources (e.g., inter-block interconnect) will not be exhausted by complex designs. It is also desirable to have a CPLD whose architecture eases the partitioning, placement, and routing chores of CPLD-configuring software.
Aside from speed and full function implementation, users of CPLD""s also usually want a certain degree of re-design agility (flexibility). Even after an initial design is successfully implemented by a CPLD, users may wish to make slight tweaks or other changes to their original design. The re-design agility of a given CPLD architecture may include the ability to re-design certain internal circuits without changing I/O timings. Re-design agility may also include the ability to re-design certain internal circuits without changing the placement of various I/O terminals (e.g., pins). Such re-design agilities are sometimes referred to respectively as re-design Speed-Locking(trademark) and Pin-Retention (the former term is a trademark of Lattice Corp., headquartered in Hillsboro, Oreg.). The more generic terms of: xe2x80x98re-design Speed-Consistencyxe2x80x99 and xe2x80x98re-design PinOut-Consistencyxe2x80x99 or xe2x80x98terminal-retentionxe2x80x99 may be respectively used herein interchangeably with xe2x80x98re-design Speed-Locking(trademark)xe2x80x99 and xe2x80x98re-design Pin-Retentionxe2x80x99.
In addition to speed, re-design agility, and full Boolean correctness, users of CPLD""s typically ask for optimal emulation of an original design or a re-design in terms of good function packing density, low cost, low power usage, synchronous signal flow, and so forth. It is not a trivial matter to satisfy all these desires because often times they conflict with one another. One solution for trying to satisfy these conflicting desires is presented by the unique macrocell design of the above-cited, U.S. Pat. No. 6,150,841. One or more improvements over that macrocell design are disclosed herein.
Structures and methods may be provided in accordance with the present disclosure of invention for improving over the above-described macrocell design and/or providing other advancements over prior CPLD designs.
(A) More specifically, in accordance with one set of aspects of the present disclosure, techniques are provided for allowing one or more of the following:
1) Elective use of a fast, allocator-bypassing path (e.g., fast 5-PT path) in combination with in-block simple or super-allocation;
2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency (pin-retention);
3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes;
4) Global distribution of globally-usable output enable signals;
5) Elective use of two-stage steering to develop complex sum-of-clusters terms; and
6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 20 or less macrocell units per logic block.
(B) In accordance with a second aspect of the present disclosure, techniques are provided for concentrating the development of complex function signals (e.g., xe2x89xa680 PT""s) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources.
A CPLD configuring method in accordance with the present disclosure may include the machine-implemented steps of first identifying middle-complexity functions that are to be implemented by the CPLD where each such middle-complexity function is achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; second identifying for those middle-complexity functions that satisfy the first identification criteria, those that have critical timing constraints that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first and second identification steps by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.
Other aspects of the disclosure will become apparent from the below detailed description.